1. Field of the Invention
The present invention relates to conductive planes within an integrated circuit carrier, such as a pin grid array package, for conveying power/ground to an integrated circuit attached to the carrier, and particularly relates to improving uniformity in current flowing through each of a plurality of external electrodes of the carrier connected to such a conductive plane.
2. Description of the Related Art
Integrated circuit carriers are well known in the art, and a wide variety of such integrated circuit carriers are readily available. Each type of carrier provides a physical body to which an integrated circuit die is attached, and usually affords a moderate to great deal of physical protection for the integrated circuit die. Frequently such integrated circuit carriers provide an enclosure having a cavity within which the die is attached and which is then covered by a protective lid. Other integrated circuit carriers protect an attached die using a molded plastic resin which surrounds the die. Typically, such carriers provide an electrical connection to the integrated circuit attached to the carrier by way of a number of external electrodes. For certain types of xe2x80x9cleadedxe2x80x9d carriers, such as a pin-grid-array (PGA) package, the external electrodes are package pins which extend from the body of the package. An example of such a package is shown in FIG. 1, which shows an integrated circuit carrier 100 having a body 102 and a number of external pins (one of which is labeled 104) extending from the bottom surface of the body 102. Other types of carriers provide external electrodes which are accessible on the surface of the carrier body, as with many xe2x80x9cleadlessxe2x80x9d chip carriers (LCCs). Another type of package is shown in FIG. 2, which shows a ball-grid-array package 110, having a ceramic body 112 and a number of external compressible xe2x80x9cballsxe2x80x9d (one of which is labeled 114) extending from the bottom surface of the body 112.
PGA packages are readily available in both ceramic and plastic versions. While these package types are well known in the art, for clarity an orthogonal view of a ceramic PGA package is illustrated in FIG. 3, while an orthogonal view of a plastic PGA package is illustrated in FIG. 4.
As is well known in the art, integrated circuit carriers frequently include multiple wiring layers for making electrical interconnections within the carrier. Some of these layers may be arranged to provide a number of respective interconnections between a respective external electrode and a respective internal contact pad, and are typically used to route signals to or from the integrated circuit. The internal contact pads of the carrier may be arranged to provide for wire bond connections between the internal contact pads of the carrier and the bond pads within the integrated circuit die. Alternatively, the internal contact pads may be arranged to provide for solder bump connections to the die. Other layers may be arranged to provide one or more large planar conductive areas within the layer. Frequently such a conductive plane occupies an entire layer, and is often used to convey a power supply voltage (or a xe2x80x9cgroundxe2x80x9d reference voltage) received on one or more external electrodes to one or more internal contact pads, which then are connected to the die by way of wire bonds, solder bumps, or other structures. In its simplest form, an integrated circuit carrier need only include one wiring layer, but most high performance carriers usually include several wiring layers. Vias are used within the carrier to couple a trace on one layer to a trace on another layer (or to a conductive plane).
Conductive planes are also frequently incorporated into portions of one or more wiring layers within an integrated circuit carrier. Such conductive planes provide an effective way to convey power supply voltages (as well as a xe2x80x9cgroundxe2x80x9d reference voltage) to integrated circuit in a manner that has both low impedance and low inductance. These conductive planes are frequently called xe2x80x9cpower planesxe2x80x9d irrespective of whether an actual xe2x80x9cpower supplyxe2x80x9d voltage, a xe2x80x9cgroundxe2x80x9d reference voltage, an analog reference voltage, or some other voltage is actually conveyed on the conductive plane. As used herein, the term xe2x80x9cpower planexe2x80x9d should not be viewed as suggesting that a xe2x80x9cpower supplyxe2x80x9d voltage need be conveyed on such a power plane. In some cases, an entire wiring layer is utilized to provide a conductive plane for a particular power supply voltage or ground potential. In other cases, a portion of a wiring layer is used to provide a conductive plane in a region of the carrier.
The power consumption of many integrated circuit devices has increased as a result of ever higher levels of integration, and ever increasing speeds achievable. As a result, devices are commonly available having power dissipations that previously would have been unprecedented. For example, high performance processor devices today dissipate tens of watts and require packages having hundreds of pins. Even with dozens of package pins allocated to each major power supply voltage (e.g., internal VSS (source voltage from external power supply), I/O buffer VSS, internal VDD (drain voltage from external power supply), etc.) the magnitude of the current flowing through each of the power pins of the carrier must not exceed the maximum current specified for either the package or for the connector into which the package is inserted. Most connectors, by design, specify an upper limit for the magnitude of current flowing through each such pin. In some cases, modern connectors are limited to no more than one ampere (i.e., 1 A) of current per connector pin. Even with a large number of pins within the package allocated as power pins for a given power supply or ground connection to a power plane within a printed wiring board, the design of both the integrated circuit die and the package (and at times, the printed wiring board) must ensure that each such power pin conducts a current no higher than the design limit for the particular package and/or connector utilized.
While such maximum current flow limits may be problematic for many kinds of integrated circuits, the problems are particularly worrisome in the case of modern CPU devices, where the amount of current consumed is typically so much greater than with other kinds of devices. Previously, the current limitations per power pin were rarely exceeded, even when scant attention was paid to the amount of current flowing through each power pin. However, as devices conducting far higher currents than in the past are more widely utilized, additional care is needed to ensure that the maximum current per connector pin is not exceeded.
As an example, high performance microprocessor integrated circuits are frequently assembled into pin grid array packages (PGAs) and inserted into a pin grid array socket on a motherboard. The current demanded by such a microprocessor flows from a regulator (or regulator connection) on the motherboard, through the socket, through the pins of the PGA, through one or more power planes within the PGA, then through solder bump connections to xe2x80x9cbonding padsxe2x80x9d of the integrated circuit die itself. Similarly, the ground return current flows from the integrated circuit die, through the solder bumps, power planes, and connector pins, and then to the motherboard. When using motherboards and packages with high conductivity power planes ( less than 1 milliOhm per square), the resistance of the PGA pin sockets (usually about 10 milliOhms) will dominate and the current flow will be relatively well distributed among the various PGA pins allocated to the power plane. However, ceramic PGA packages have significantly higher power plane resistance (e.g., 10 milliOhm per square) which significantly affects the pattern of current flow in the package power planes.
Thicker power planes within the package reduce the effective resistance per square of the power plane, and help distribute the current more evenly to a greater number of power pins of the package. Similarly, the use of multiple power planes in parallel also achieves a lower effective resistance. But such options are not always available when designing packages.
In spite of the long history of package designs that accommodate high pin-count and relatively high-current devices, the particular problems of high current flow through package and/or connector power pins become more difficult with each new generation of microprocessors. Consequently, there is a continuing need for improvements in package design.
Even though an integrated circuit package has a large number of power pins allocated to an internal power plane, the current flowing through the power pins may divide very unevenly, and result in current flow through some of the power pins which exceeds the maximum specification for either the package pin or for the socket into which the package may be inserted. Current flow is much higher through those package pins having a conductive path to one or more of the internal contact pads whose impedance is lower than most of the others. Because the power plane in a printed wiring board to which the package is frequently connected is typically so much lower in impedance than that of the power planes within the package, current flowing from the internal contact pads to the package pins tends to xe2x80x9cdivexe2x80x9d down to the motherboard along the path of least resistance, which path xe2x80x9chogsxe2x80x9d more than the particular package pin""s proportionate share of the total current. The min-to-max current ratio may easily be as high as 1:4, with the highest current package pins well above 1 ampere in current.
The magnitude of the current flowing through the highest current package pins is reduced by configuring the resistance of the pins, the power plane, and vias to provide approximately the same total resistance to every power pin location. Slots may be cut in one of the power planes to alter the current path and raise the impedance of the conduction path between some of the package pins and the internal contact pads otherwise having the lowest impedance. If the package includes more than one row of pins along an edge of the package, the internal package vias may be arranged to provide an impedance from die location to the outer row of pins which is not substantially higher than that of the inner row of pins.
In this fashion the aggregate current carrying capacity of a PGA package may be increased by reducing the difference in current flow between power pins having the highest current flow and power pins having the lowest current flow. The current flow through all the power pins may then be operated nearer to the design maximum of the particular connector used, or the design maximum of the package itself.
The present invention may be better understood, and its numerous features and advantages made even more apparent to those skilled in the art by referencing the detailed description and accompanying drawings of the embodiments described below. These and other embodiments of the present invention are defined by the claims appended hereto.